Fast, Energy Efficient 6T SRAM Arrays using Harvested Data

CMOS harvesting circuits are disclosed for conventional 6T SRAM bitcell arrays enabling substantial improvements to SRAM access time, pipeline performance and to SRAM active and leakage energy consumption-without scaling operating voltages while also improving Read and Write margins using assist sch...

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Bibliographische Detailangaben

1. Verfasser:	Bhavnagarwala, Azeez
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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