Fast, Energy Efficient 6T SRAM Arrays using Harvested Data

CMOS harvesting circuits are disclosed for conventional 6T SRAM bitcell arrays enabling substantial improvements to SRAM access time, pipeline performance and to SRAM active and leakage energy consumption-without scaling operating voltages while also improving Read and Write margins using assist schemes at very low area and energy overhead by reusing circuits that harvest charge. Active energy dissipation during an SRAM read access is lowered by use of novel sensing schemes that self-limit signal development on the BL without the energy overheads seen in conventional designs from sense-amp offsets, BL column leakage and uncertain read current. Improvements in access time are enabled by increasing the signal development rate on the BL-by comparing the rising electric potential of harvested charge with a decreasing BL voltage in a bitcell column using a novel and compact inverting amplifier with dynamic reset. This area and energy efficient scheme leveraging availability of harvested charge not only self-limits signal development on the BL to lower active power and improve read latency, but also eliminates most of the uncertainty of BL voltage signal from uncertain read current by using a capacitive divider. Charge harvested in each column of bitcells from a read/write access is moved to a local harvest grid with a fraction of the capacitance of the BLs accessed in the subarray, at a voltage closer to VDD and is readily tapped into during a following Write access lowering write energy consumption from the power grid by over 30%. Active or standby mode leakage is lowered by the raised voltage of the harvesting node in each column-that is discharged only before the WL selects -for all columns during a Read and for half-select columns during a Write