Interfacial Layer Between Fin and Source/Drain Region

Interfacial Layer Between Fin and Source/Drain Region

An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain reg...

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Bibliographische Detailangaben
Hauptverfasser: Sung, Hsueh-Chang, Liu, Davie, Li, Chii-Horng, Tai, Roger, Lin, Yan-Ting, Chin, Chih-Yun, Lee, Chien-Wei, Lee, Yen-Ru, Jeng, Pei-Ren, Hsu, Tzu-Hsiang, Ting, Heng-Wen
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.