ADJUSTABLE TIMER COMPONENT FOR SEMICONDUCTOR DEVICES

Systems, apparatuses, and methods related to an adjustable timer component are described. A memory device includes, a memory controller coupled to the memory device comprising an adjustable timer component. The adjustable timer component is configured to receive a timer generation request and, responsive to receiving the request, store in a cache an active timer entry corresponding to a particular first address, generate a timer corresponding to an active timer entry and the particular first address, and monitor the timer to determine when the timer expires. Responsive to the expiration of the timer, dequeue the timer entry and invalidate the timer entry stored in the cache. The memory device can also include command logic configured to, prior to issuing a second command, query the cache of the adjustable timer component to determine if the cache includes an active timer entry corresponding to the particular second address.