REAL-EQUIVALENT-TIME FLASH ARRAY DIGITIZER OSCILLOSCOPE ARCHITECTURE

A test and measurement system includes a clock recovery circuit configured to receive a signal from a device under test and to produce a pattern trigger signal, a flash array digitizer having an array of counters having rows and columns configured to store a waveform image representing the signal received from the device under test, a row selection circuit configured to select a row in the array of counters, and a ring counter circuit configured to receive a clock signal, select a column in the array of counters, produce end of row signals, and produce a fill complete signal upon all of the columns having been swept, the fill complete signal indicating completion of the waveform image, an equivalent time sweep logic circuit configured to receive the pattern trigger signal and the end of row signals from the ring counter and to produce the clock signal with a delay to increment a clock delay to the ring counter until the fill complete signal is received, and a machine learning system configured to receive the waveform image and provide operating parameters for the device under test. A test and measurement system includes a flash array digitizer having an array of counters having rows and columns configured to store a waveform image representing a signal received from a device under test, a row selection circuit configured to select a row in the array of counters, a column selection circuit configured to select a column in the array of counters, a sample clock connected to the row selection circuit and the column selection circuit, and a machine learning system configured to receive the waveform image from the flash array digitizer and provide operating parameters for the device under test.