DIVIDING CIRCUIT SYSTEM AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THEREOF
A dividing circuit system includes a first dividing circuit and a second dividing circuit. The first dividing circuit performs a reset operation based on a reset control signal and generates second and fourth divided clock signals. The second dividing circuit performs a reset operation based on the...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | A dividing circuit system includes a first dividing circuit and a second dividing circuit. The first dividing circuit performs a reset operation based on a reset control signal and generates second and fourth divided clock signals. The second dividing circuit performs a reset operation based on the reset control signal and generates first and third divided clock signals. |
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