BUILT-IN SELF TEST CIRCUIT FOR MEASURING PHASE NOISE OF A PHASE LOCKED LOOP

An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (ΔΣ) time-to-digital converter (TDC) are disclosed. In some embodiments,...

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Bibliographische Detailangaben
Hauptverfasser:	CHANG, Chih-Hsien, CHANG, Ya-Tin, CHOU, Mao-Hsuan, SHEEN, Ruey-Bin
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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Beschreibung
Zusammenfassung:	An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (ΔΣ) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ΔΣ TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ΔΣ TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ΔΣ TDC, wherein the MASH type high-order ΔΣ TDC is configured to measure the phase noise of a device under text (DUT).