CLOCKING ARCHITECTURE FOR A MULTI-DIE PACKAGE

A device including a system phase lock loop circuit to: receive a primary reference clock, generate a reference clock from the primary reference clock, and transmit the reference clock; and a phase lock loop circuit to receive the reference clocks, generate a sub-reference clock from the received re...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	Nalamalpu, Ankireddy, Maheshwari, Atul, Kumashikar, Mahesh K, Tang, Lai Guan
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY
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Beschreibung
Zusammenfassung:	A device including a system phase lock loop circuit to: receive a primary reference clock, generate a reference clock from the primary reference clock, and transmit the reference clock; and a phase lock loop circuit to receive the reference clocks, generate a sub-reference clock from the received respective reference clocks, and transmit the sub-reference clock from the phase lock loop circuit to drive operation of a first chiplet using the respective sub-reference clock, wherein the sub-reference clock drives the first chiplet.