POWER AND PERFORMANCE OPTIMIZATION IN A MEMORY SUBSYSTEM

Hardware and/or software that dynamically enables or disables CRC and/or adjust voltage level of power supply to a physical layer block on a host by determining an optimum tradeoff between power and performance. The hardware and/or software decreases the voltage level for the power supply and enable...

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Hauptverfasser:	Mathiyalagan, Vijay Anand, Mitra, Sambaran
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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creator	Mathiyalagan, Vijay Anand Mitra, Sambaran
description	Hardware and/or software that dynamically enables or disables CRC and/or adjust voltage level of power supply to a physical layer block on a host by determining an optimum tradeoff between power and performance. The hardware and/or software decreases the voltage level for the power supply and enables CRC to compensate signal errors (e.g., errors from signal integrity issues). Hardware and/or software dynamically adjusts voltage level of the power supply rail based on the throughput or speed of the DDR link. In some examples, depending on read or write operations, the voltage level of the power supply rail is adjusted.
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The hardware and/or software decreases the voltage level for the power supply and enables CRC to compensate signal errors (e.g., errors from signal integrity issues). Hardware and/or software dynamically adjusts voltage level of the power supply rail based on the throughput or speed of the DDR link. In some examples, depending on read or write operations, the voltage level of the power supply rail is adjusted.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220623&DB=EPODOC&CC=US&NR=2022199142A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220623&DB=EPODOC&CC=US&NR=2022199142A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Mathiyalagan, Vijay Anand</creatorcontrib><creatorcontrib>Mitra, Sambaran</creatorcontrib><title>POWER AND PERFORMANCE OPTIMIZATION IN A MEMORY SUBSYSTEM</title><description>Hardware and/or software that dynamically enables or disables CRC and/or adjust voltage level of power supply to a physical layer block on a host by determining an optimum tradeoff between power and performance. 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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
title	POWER AND PERFORMANCE OPTIMIZATION IN A MEMORY SUBSYSTEM
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