SYSTOLIC ARRAY CELLS WITH MULTIPLE ACCUMULATORS

This specification describes systolic arrays of hardware processing units. In one aspect, a matrix computation unit includes multiple cells arranged in a systolic array. Each cell includes multiplication circuitry configured to determine a product of elements or submatrices of input matrices, summation circuitry configured to determine a sum of an input accumulated value and the product output by the multiplication circuitry, multiple accumulators connected to an output of the summation circuitry, and a controller circuit configured to select, from the accumulators, a given accumulator to receive the sum output by the summation circuitry.