INTERFACE OF A MEMORY CIRCUIT AND MEMORY SYSTEM THEREOF

INTERFACE OF A MEMORY CIRCUIT AND MEMORY SYSTEM THEREOF

An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage for enabling the memory circuit. The at least one data terminal...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: MA, LIN, MA, HUNG-PIAO, LIN, CHUN YI, WONG, KENG LONE, CHEN, WENLIANG, NANJAPPA, GIRISH
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage for enabling the memory circuit. The at least one data terminal receives at least one first data signal that varies between a second high voltage and the low voltage. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage. The first data strobe signal is synchronized with the at least one first data signal, and is arranged to latch and sample the at least one first data signal. The first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage.