Active N-Well Switching Circuit for Power Switches

An n-well voltage switching circuit (60) and methodology are disclosed for generating a maximum bias voltage (VMAX) at the output voltage node with cross-coupled PMOS switching transistors (63) connected to a voltage supply remapping circuit (61, 62, 64) which receives first and second power supplies (VSUP1, VSUP2) and generates first and second gate driving signals (G1, G4), wherein the first and second gate driving signals are connected, respectively, to the gates of the first and second cross-coupled PMOS transistors (P5, P6) to pull a gate for one of the cross-coupled PMOS transistors to ground so that the higher of the first and second power supplies is coupled to the output voltage node over one of the first and second cross-coupled PMOS transistors, thereby generating a maximum bias voltage at the output voltage node.