VIA CONNECTIONS FOR STAGGERED INTERCONNECT LINES
Via connections for staggered interconnect lines are disclosed. An interconnect structure includes a first plurality of interconnects and a second plurality of interconnects, wherein the first plurality of interconnects and the second plurality of interconnects are staggered such that individual int...
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creator | JEZEWSKI, Christopher J LIN, Kevin Lai |
description | Via connections for staggered interconnect lines are disclosed. An interconnect structure includes a first plurality of interconnects and a second plurality of interconnects, wherein the first plurality of interconnects and the second plurality of interconnects are staggered such that individual interconnects of the second plurality of interconnects are laterally offset from individual interconnects of the first plurality of interconnects. The interconnect structure also includes a via coupling an individual interconnect of the first plurality of interconnects to an individual interconnect of the second plurality of interconnects. |
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An interconnect structure includes a first plurality of interconnects and a second plurality of interconnects, wherein the first plurality of interconnects and the second plurality of interconnects are staggered such that individual interconnects of the second plurality of interconnects are laterally offset from individual interconnects of the first plurality of interconnects. The interconnect structure also includes a via coupling an individual interconnect of the first plurality of interconnects to an individual interconnect of the second plurality of interconnects.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220324&DB=EPODOC&CC=US&NR=2022093505A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220324&DB=EPODOC&CC=US&NR=2022093505A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JEZEWSKI, Christopher J</creatorcontrib><creatorcontrib>LIN, Kevin Lai</creatorcontrib><title>VIA CONNECTIONS FOR STAGGERED INTERCONNECT LINES</title><description>Via connections for staggered interconnect lines are disclosed. An interconnect structure includes a first plurality of interconnects and a second plurality of interconnects, wherein the first plurality of interconnects and the second plurality of interconnects are staggered such that individual interconnects of the second plurality of interconnects are laterally offset from individual interconnects of the first plurality of interconnects. The interconnect structure also includes a via coupling an individual interconnect of the first plurality of interconnects to an individual interconnect of the second plurality of interconnects.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAI83RUcPb383N1DvH09wtWcPMPUggOcXR3dw1ydVHw9AtxDYJKK_h4-rkG8zCwpiXmFKfyQmluBmU31xBnD93Ugvz41OKCxOTUvNSS-NBgIwMjIwNLY1MDU0dDY-JUAQDQqidK</recordid><startdate>20220324</startdate><enddate>20220324</enddate><creator>JEZEWSKI, Christopher J</creator><creator>LIN, Kevin Lai</creator><scope>EVB</scope></search><sort><creationdate>20220324</creationdate><title>VIA CONNECTIONS FOR STAGGERED INTERCONNECT LINES</title><author>JEZEWSKI, Christopher J ; LIN, Kevin Lai</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022093505A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JEZEWSKI, Christopher J</creatorcontrib><creatorcontrib>LIN, Kevin Lai</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JEZEWSKI, Christopher J</au><au>LIN, Kevin Lai</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>VIA CONNECTIONS FOR STAGGERED INTERCONNECT LINES</title><date>2022-03-24</date><risdate>2022</risdate><abstract>Via connections for staggered interconnect lines are disclosed. An interconnect structure includes a first plurality of interconnects and a second plurality of interconnects, wherein the first plurality of interconnects and the second plurality of interconnects are staggered such that individual interconnects of the second plurality of interconnects are laterally offset from individual interconnects of the first plurality of interconnects. The interconnect structure also includes a via coupling an individual interconnect of the first plurality of interconnects to an individual interconnect of the second plurality of interconnects.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | VIA CONNECTIONS FOR STAGGERED INTERCONNECT LINES |
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