METHOD FOR IDENTIFYING PCB CORE-LAYER PROPERTIES

A reference via in a set of plated vias on a printed circuit board is located. A reference lead is applied to the reference via. A test via in the set of plated vias is located. A test lead is applied to the test via. An electrical conductance between the reference via and the test via is measured....

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Bibliographische Detailangaben
Hauptverfasser:	Hu, Xiao, Yin, XiYuan, Yang, Zhongfeng, Li, Mingman, Song, Tao, Mu, LiCen
Format:	Patent
Sprache:	eng
Schlagworte:	CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS PRINTED CIRCUITS TESTING
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Beschreibung
Zusammenfassung:	A reference via in a set of plated vias on a printed circuit board is located. A reference lead is applied to the reference via. A test via in the set of plated vias is located. A test lead is applied to the test via. An electrical conductance between the reference via and the test via is measured. A property of a core layer of the printed circuit board is identified based on the electrical conductance.