SECURE AND CONFIGURABLE TEST INTERACE FOR AN INTELLECTUAL PROPERTY (IP) BLOCK IN A SYSTEM ON A CHIP (SOC)

A design for test (DFT) block of a system on a chip (SOC) includes a function mapping interface coupled to a set of function interfaces of an intellectual property (IP) block core; and a core coupled to the function mapping interface by a plurality of test interfaces, the core including an interpose...

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Hauptverfasser:	Martinez, Alfonso Tarazona, Gopala Rao, Shravan Kumar Hossur, Hogan, Mark, Walsh, Gordon, Hunt, Allyn, Ravinarayanan, Balajiraja, Calle, Ruben Trejo, Morgan, Michael
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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creator	Martinez, Alfonso Tarazona Gopala Rao, Shravan Kumar Hossur Hogan, Mark Walsh, Gordon Hunt, Allyn Ravinarayanan, Balajiraja Calle, Ruben Trejo Morgan, Michael
description	A design for test (DFT) block of a system on a chip (SOC) includes a function mapping interface coupled to a set of function interfaces of an intellectual property (IP) block core; and a core coupled to the function mapping interface by a plurality of test interfaces, the core including an interposer to manage assignments of the plurality of test interfaces from the function mapping interface to a plurality of placeholder interfaces of a collar, wherein the function mapping interface maps the set of function interfaces to the plurality of test interfaces.
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and a core coupled to the function mapping interface by a plurality of test interfaces, the core including an interposer to manage assignments of the plurality of test interfaces from the function mapping interface to a plurality of placeholder interfaces of a collar, wherein the function mapping interface maps the set of function interfaces to the plurality of test interfaces.</abstract><oa>free_for_read</oa></addata></record>
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
title	SECURE AND CONFIGURABLE TEST INTERACE FOR AN INTELLECTUAL PROPERTY (IP) BLOCK IN A SYSTEM ON A CHIP (SOC)
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