SECURE AND CONFIGURABLE TEST INTERACE FOR AN INTELLECTUAL PROPERTY (IP) BLOCK IN A SYSTEM ON A CHIP (SOC)

A design for test (DFT) block of a system on a chip (SOC) includes a function mapping interface coupled to a set of function interfaces of an intellectual property (IP) block core; and a core coupled to the function mapping interface by a plurality of test interfaces, the core including an interpose...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Martinez, Alfonso Tarazona, Gopala Rao, Shravan Kumar Hossur, Hogan, Mark, Walsh, Gordon, Hunt, Allyn, Ravinarayanan, Balajiraja, Calle, Ruben Trejo, Morgan, Michael
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	A design for test (DFT) block of a system on a chip (SOC) includes a function mapping interface coupled to a set of function interfaces of an intellectual property (IP) block core; and a core coupled to the function mapping interface by a plurality of test interfaces, the core including an interposer to manage assignments of the plurality of test interfaces from the function mapping interface to a plurality of placeholder interfaces of a collar, wherein the function mapping interface maps the set of function interfaces to the plurality of test interfaces.