UP-DIFFUSION SUPPRESSION IN A POWER MOSFET

UP-DIFFUSION SUPPRESSION IN A POWER MOSFET

A substrate for fabricating a MOSFET device includes a first epitaxial layer disposed on a silicon wafer. The silicon wafer is doped with a first dopant. A second epitaxial layer is disposed on the first epitaxial layer. An ion-implanted capping layer is disposed in the first epitaxial layer. The io...

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Bibliographische Detailangaben
1. Verfasser: VENKATRAMAN, Prasad
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Zusammenfassung:A substrate for fabricating a MOSFET device includes a first epitaxial layer disposed on a silicon wafer. The silicon wafer is doped with a first dopant. A second epitaxial layer is disposed on the first epitaxial layer. An ion-implanted capping layer is disposed in the first epitaxial layer. The ion-implanted capping layer is doped with a second dopant. The first dopant has a diffusion coefficient in silicon higher than a diffusion coefficient of the second dopant in silicon. The ion-implanted capping layer is configured to limit up-diffusion of the first dopant from the silicon wafer into the second epitaxial layer.