SYSTEM AND METHOD FOR LOW JITTER PHASE-LOCK LOOP BASED FREQUENCY SYNTHESIZER

The disclosed systems, structures, and methods are directed to a low jitter phase-lock loop (PLL) based frequency synthesizer, comprising a first frequency divider, a phase frequency detector, a charge pump, a low-pass filter, a voltage control oscillator (VCO), a phase interpolator communicatively coupled in a feedback path between the VCO and the phase frequency detector, wherein the phase interpolator comprises a quadrature generator, an input conditioner, a phase rotator, a current mode logic (CML), and a second frequency divider communicatively coupled in the feedback path between the phase interpolator and the phase frequency detector.