MEMORY ACCESS TECHNIQUES IN MEMORY DEVICES WITH MULTIPLE PARTITIONS

MEMORY ACCESS TECHNIQUES IN MEMORY DEVICES WITH MULTIPLE PARTITIONS

Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a cur...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Sundaram, Rajesh, Qawami, Shekoufeh
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a command/address (C/A) bus, which may have a relatively low pin count, through use of a next partition command that may repeat an array command from a current partition at a different partition indicated by the next partition command. Such a next partition command may use fewer clock cycles than a command that includes a complete instruction and memory location information.