METHODS AND APPARATUS FOR BOOT TIME REDUCTION IN A PROCESSOR AND PROGRAMMABLE LOGIC DEVICE ENVIROMENT

Methods and apparatus for boot time reduction in a processor and programmable logic device environment are disclosed. An example apparatus includes a multicore processor including a first core and a second core. A bootstrap processor is to initialize the first core into a standby mode and initialize the second core into a non-standby mode. A programmable logic device is to be programmed with instructions to be executed by the programmable logic device by the second core via a first connection initialized by the second core. The bootstrap processor is to, upon completion of the programming of the programmable logic device, initialize a data connection between the programmable logic device and the second core.