IN-MEMORY DEVICE FOR OPERATING MULTI-BIT WEIGHT

IN-MEMORY DEVICE FOR OPERATING MULTI-BIT WEIGHT

Disclosed is an in-memory device for operation of a multi-bit weight. A multi-bit memory cell array according to an exemplary embodiment of the present invention includes at least one multi-bit unit which stores input data based on an input signal and outputs a per-group sum value summed for every g...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: AHN, Hong Keun, JUNG, Seong Ook, LEE, Young Kyu
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
PHYSICS
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Beschreibung
Zusammenfassung:Disclosed is an in-memory device for operation of a multi-bit weight. A multi-bit memory cell array according to an exemplary embodiment of the present invention includes at least one multi-bit unit which stores input data based on an input signal and outputs a per-group sum value summed for every group by applying a multi-bit weight to the stored input data; and a final summation unit which is connected to at least one multi-bit unit, adjusts a ratio for every group to receive the peer-group sum value, and outputs a final output value by summing the input per-group sum value.