FUSI GATED DEVICE FORMATION

Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conducti...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser:	Tuan, Hsiao-Chin, Wu, Chia-Hong, Lin, Ta-Wei, Thei, Kong-Beng, Chou, Chien-Chih, Chen, Yi-Huan, Kalnitsky, Alexander
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conductive layer. A bottom surface of the polysilicon layer is aligned with a bottom surface of the conductive layer. A dielectric layer overlies the polysilicon layer. The dielectric layer continuously extends from sidewalls of the polysilicon layer to an upper surface of the conductive layer.