ERROR CORRECTION ON A MEMORY DEVICE

Methods, systems, and devices for error correction on a memory device are described. Examples may include a memory die having an array of memory cells including a plurality of banks. The memory die may further include a first error correcting code (ECC) circuit coupled with a first bank of memory ce...

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Bibliographische Detailangaben
1. Verfasser:	Porter, John David
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING CODE CONVERSION IN GENERAL CODING COMPUTING COUNTING DECODING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES
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Beschreibung
Zusammenfassung:	Methods, systems, and devices for error correction on a memory device are described. Examples may include a memory die having an array of memory cells including a plurality of banks. The memory die may further include a first error correcting code (ECC) circuit coupled with a first bank of memory cells, where the first ECC circuit is configured to perform operations associated with a first access operation (e.g., write operation) of the first bank of memory cells. The memory die may further include a second ECC circuit coupled with the first bank of memory cells, where the second ECC circuit is configured to perform ECC operations associated with a second access operation (e.g., read operation) of the first bank. In some cases, the first ECC circuit may be located under the footprint of the array and the second ECC circuit may be located outside the footprint of the array.