ARITHMETIC PROCESSING APPARATUS

An arithmetic processing apparatus includes two instruction decoders. A first decoder processes instructions in a single cycle, while a second decoder processes instructions in a plurality of cycles. The apparatus further includes a determination circuit that causes the first decoder to process an instruction to be processed when the instruction to be processed is a specific instruction and there is no previous instruction being processed, and causes the second decoder to process the instruction to be processed when the instruction to be processed is not the specific instruction or there is a previous instruction being processed.