MEMORY ARCHITECTURE WITH SHARED BITLINE AT BACK-END-OF-LINE

Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control...

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Bibliographische Detailangaben
Hauptverfasser:	SELL, Bernhard, SHARMA, Abhishek A, PIERCE, Kimberly L, WANG, Pei-Hua, CHEN, Yu-Jin, TAN, Elliot N, LE, Van H, ALZATE VINASCO, Juan G, LAJOIE, Travis W
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.