Embedded PHY (EPHY) IP Core for FPGA

The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYs (MPHYs), to meet universal f...

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Bibliographische Detailangaben
Hauptverfasser:	LERNER, Eitan, GANON, Doron
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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Beschreibung
Zusammenfassung:	The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYs (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.