TESTING ADDRESS TRANSLATION CACHE

A method, apparatus and product for utilizing address translation structures for testing address translation cache. The method comprises: obtaining a first address translation structure that comprises multiple levels, including a first top level which connects a sub-structure of the first address translation structure using pointers thereto; determining, based on the first address translation structure, a second address translation structure, wherein the second address translation structure comprises a second top level that is determined based on the first top level, wherein the second top level connects the sub-structure of the first address translation structure; executing a test so as to verify operation of an address translation cache of a target processor at least by: adding a plurality of cache lines to the address translation cache, wherein said adding is based on the address translation structures; and verifying the operation of the address translation cache using one or more memory access operations.