SILICIDATION OF SOURCE/DRAIN REGION OF VERTICAL FIELD EFFECT TRANSISTOR (VFET) STRUCTURE

SILICIDATION OF SOURCE/DRAIN REGION OF VERTICAL FIELD EFFECT TRANSISTOR (VFET) STRUCTURE

A vertical field effect transistor (VFET) structure includes: a substrate; fin structures formed on the substrate; bottom source/drain regions formed on the substrate between and at opposite sides of lower portions of the fin structures; and shallow trench isolation (STI) structures formed at sides...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Kim, Min Gyu, Jun, Hwi Chan
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A vertical field effect transistor (VFET) structure includes: a substrate; fin structures formed on the substrate; bottom source/drain regions formed on the substrate between and at opposite sides of lower portions of the fin structures; and shallow trench isolation (STI) structures formed at sides of the substrate and the bottom source/drain regions, wherein upper portions of the bottom source/drain regions include silicide layers each of which has a bar shape.