COLUMN SELECT SWIZZLE
A memory device includes a memory array having a plurality of memory cells and a column decoder circuit that is configured to provide at least one column select signal for selecting corresponding bit-lines for memory operations on the plurality of memory cells. The memory device also includes a colu...
Gespeichert in:
| Hauptverfasser: | , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Zusammenfassung: | A memory device includes a memory array having a plurality of memory cells and a column decoder circuit that is configured to provide at least one column select signal for selecting corresponding bit-lines for memory operations on the plurality of memory cells. The memory device also includes a column select section that is configured to route the at least one column select signal such that non-adjacent bit-lines are exclusively selected during a same column select access memory operation. |
|---|