DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT

A delay line includes first to n-th delay cells and a dummy delay cell, 'n' being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to nth output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n−1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding to delay cell, and a delay amount of the nth delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.