ADJUSTABLE NAND WRITE PERFORMANCE

Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell b...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Cariello, Giuseppe, Falduti, Stefano, Sali, Mauro Luigi, Russo, Ugo
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Cariello, Giuseppe
Falduti, Stefano
Sali, Mauro Luigi
Russo, Ugo
description Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2021141530A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2021141530A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2021141530A13</originalsourceid><addsrcrecordid>eNrjZFB0dPEKDQ5xdPJxVfBz9HNRCA_yDHFVCHANcvMP8nX0c3blYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkaGhiaGpsYGjobGxKkCAJugIv8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ADJUSTABLE NAND WRITE PERFORMANCE</title><source>esp@cenet</source><creator>Cariello, Giuseppe ; Falduti, Stefano ; Sali, Mauro Luigi ; Russo, Ugo</creator><creatorcontrib>Cariello, Giuseppe ; Falduti, Stefano ; Sali, Mauro Luigi ; Russo, Ugo</creatorcontrib><description>Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210513&amp;DB=EPODOC&amp;CC=US&amp;NR=2021141530A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210513&amp;DB=EPODOC&amp;CC=US&amp;NR=2021141530A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Cariello, Giuseppe</creatorcontrib><creatorcontrib>Falduti, Stefano</creatorcontrib><creatorcontrib>Sali, Mauro Luigi</creatorcontrib><creatorcontrib>Russo, Ugo</creatorcontrib><title>ADJUSTABLE NAND WRITE PERFORMANCE</title><description>Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFB0dPEKDQ5xdPJxVfBz9HNRCA_yDHFVCHANcvMP8nX0c3blYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkaGhiaGpsYGjobGxKkCAJugIv8</recordid><startdate>20210513</startdate><enddate>20210513</enddate><creator>Cariello, Giuseppe</creator><creator>Falduti, Stefano</creator><creator>Sali, Mauro Luigi</creator><creator>Russo, Ugo</creator><scope>EVB</scope></search><sort><creationdate>20210513</creationdate><title>ADJUSTABLE NAND WRITE PERFORMANCE</title><author>Cariello, Giuseppe ; Falduti, Stefano ; Sali, Mauro Luigi ; Russo, Ugo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2021141530A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Cariello, Giuseppe</creatorcontrib><creatorcontrib>Falduti, Stefano</creatorcontrib><creatorcontrib>Sali, Mauro Luigi</creatorcontrib><creatorcontrib>Russo, Ugo</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Cariello, Giuseppe</au><au>Falduti, Stefano</au><au>Sali, Mauro Luigi</au><au>Russo, Ugo</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ADJUSTABLE NAND WRITE PERFORMANCE</title><date>2021-05-13</date><risdate>2021</risdate><abstract>Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2021141530A1
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title ADJUSTABLE NAND WRITE PERFORMANCE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T15%3A25%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Cariello,%20Giuseppe&rft.date=2021-05-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2021141530A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true