OVERLAY OPTIMIZATION

The present disclosure generally relates to semiconductor structures and, more particularly, to overlay optimization and methods of manufacture. The method includes performing, by a computing device, an exposure with a correction parameter to a first wafer; performing, by the computing device, a dec...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: KRUMANOCKER, Ian R, GOOD, Richard P
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:The present disclosure generally relates to semiconductor structures and, more particularly, to overlay optimization and methods of manufacture. The method includes performing, by a computing device, an exposure with a correction parameter to a first wafer; performing, by the computing device, a decorrection of the correction parameter; collecting, by the computing device, overlay data in response to the exposure and the decorrection; estimating, by the computing device, an optimal parameter from the overlay data; and applying, by the computing device, the optimal parameter to a second wafer to align an overlay in the second wafer.