SEMICONDUCTOR PATTERNING

A technique of producing a stack defining a plurality of TFTs including at least source/drain electrodes and addressing lines at a source/drain level, wherein the method comprises: forming a patterned source/drain level stack comprising at least a first layer over the support substrate and a second...

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Hauptverfasser:	ASPLIN, Brian, JONGMAN, Jan
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	ASPLIN, Brian JONGMAN, Jan
description	A technique of producing a stack defining a plurality of TFTs including at least source/drain electrodes and addressing lines at a source/drain level, wherein the method comprises: forming a patterned source/drain level stack comprising at least a first layer over the support substrate and a second layer over the first layer, to define at least said source/drain electrodes and said addressing lines; depositing semiconductor channel material over at least said source/drain electrodes and said addressing lines; and patterning the layer of semiconductor channel material by a patterning process; wherein the material of the first layer is more resistant to removal by said patterning process than the material of said second layer.
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JONGMAN, Jan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2021118912A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>ASPLIN, Brian</creatorcontrib><creatorcontrib>JONGMAN, Jan</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ASPLIN, Brian</au><au>JONGMAN, Jan</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PATTERNING</title><date>2021-04-22</date><risdate>2021</risdate><abstract>A technique of producing a stack defining a plurality of TFTs including at least source/drain electrodes and addressing lines at a source/drain level, wherein the method comprises: forming a patterned source/drain level stack comprising at least a first layer over the support substrate and a second layer over the first layer, to define at least said source/drain electrodes and said addressing lines; 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subjects	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
title	SEMICONDUCTOR PATTERNING
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