SEMICONDUCTOR PATTERNING

A technique of producing a stack defining a plurality of TFTs including at least source/drain electrodes and addressing lines at a source/drain level, wherein the method comprises: forming a patterned source/drain level stack comprising at least a first layer over the support substrate and a second layer over the first layer, to define at least said source/drain electrodes and said addressing lines; depositing semiconductor channel material over at least said source/drain electrodes and said addressing lines; and patterning the layer of semiconductor channel material by a patterning process; wherein the material of the first layer is more resistant to removal by said patterning process than the material of said second layer.