NETWORK AND EDGE ACCELERATION TILE (NEXT) ARCHITECTURE

NETWORK AND EDGE ACCELERATION TILE (NEXT) ARCHITECTURE

Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device config...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: MCDONNELL, Niall D, CHILIKIN, Andrey, FLEMING, Patrick, LAKKAKULA, Naveen, MOSUR, Lokpraveen, KUTCH, Patrick G, KEATING, Brian A, KRISHNA IYER, Venkidesh, GANGA, Ilango S
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.