Via Rail Structure
The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC design layout defining a semiconductor structure having a via rail extending lengthwise in a first direction and contacting a source contact extending lengthwise in a second direc...
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| creator | Hsueh, Wang-Jung Hsieh, Tung-Heng Wang, Sheng-Hsiung Kuang, Hao Young, Bao-Ru Wu, Pang-Chi |
| description | The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC design layout defining a semiconductor structure having a via rail extending lengthwise in a first direction and contacting a source contact extending lengthwise in a second direction perpendicular to the first direction. The method further includes identifying the via rail, the source contact, a drain contact being distanced away from the source contact, and a gate structure interposing the source and drain contacts using pattern recognition on the IC design layout. The method further includes determining a position, length, and width of a jog via to be added to the IC design layout. The method further includes adding the jog via having the pre-determined length and width to the IC design layout at the pre-determined position to provide a modified IC design layout and generating a tape-out for fabricating a modified mask. |
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The method includes receiving an IC design layout defining a semiconductor structure having a via rail extending lengthwise in a first direction and contacting a source contact extending lengthwise in a second direction perpendicular to the first direction. The method further includes identifying the via rail, the source contact, a drain contact being distanced away from the source contact, and a gate structure interposing the source and drain contacts using pattern recognition on the IC design layout. The method further includes determining a position, length, and width of a jog via to be added to the IC design layout. The method further includes adding the jog via having the pre-determined length and width to the IC design layout at the pre-determined position to provide a modified IC design layout and generating a tape-out for fabricating a modified mask.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210401&DB=EPODOC&CC=US&NR=2021098369A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210401&DB=EPODOC&CC=US&NR=2021098369A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Hsueh, Wang-Jung</creatorcontrib><creatorcontrib>Hsieh, Tung-Heng</creatorcontrib><creatorcontrib>Wang, Sheng-Hsiung</creatorcontrib><creatorcontrib>Kuang, Hao</creatorcontrib><creatorcontrib>Young, Bao-Ru</creatorcontrib><creatorcontrib>Wu, Pang-Chi</creatorcontrib><title>Via Rail Structure</title><description>The present disclosure provides a method for fabricating an integrated circuit (IC). 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The method further includes adding the jog via having the pre-determined length and width to the IC design layout at the pre-determined position to provide a modified IC design layout and generating a tape-out for fabricating a modified mask.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAKy0xUCErMzFEILikqTS4pLUrlYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkaGBpYWxmaWjobGxKkCAFw1ILY</recordid><startdate>20210401</startdate><enddate>20210401</enddate><creator>Hsueh, Wang-Jung</creator><creator>Hsieh, Tung-Heng</creator><creator>Wang, Sheng-Hsiung</creator><creator>Kuang, Hao</creator><creator>Young, Bao-Ru</creator><creator>Wu, Pang-Chi</creator><scope>EVB</scope></search><sort><creationdate>20210401</creationdate><title>Via Rail Structure</title><author>Hsueh, Wang-Jung ; Hsieh, Tung-Heng ; Wang, Sheng-Hsiung ; Kuang, Hao ; Young, Bao-Ru ; Wu, Pang-Chi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2021098369A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Hsueh, Wang-Jung</creatorcontrib><creatorcontrib>Hsieh, Tung-Heng</creatorcontrib><creatorcontrib>Wang, Sheng-Hsiung</creatorcontrib><creatorcontrib>Kuang, Hao</creatorcontrib><creatorcontrib>Young, Bao-Ru</creatorcontrib><creatorcontrib>Wu, Pang-Chi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hsueh, Wang-Jung</au><au>Hsieh, Tung-Heng</au><au>Wang, Sheng-Hsiung</au><au>Kuang, Hao</au><au>Young, Bao-Ru</au><au>Wu, Pang-Chi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Via Rail Structure</title><date>2021-04-01</date><risdate>2021</risdate><abstract>The present disclosure provides a method for fabricating an integrated circuit (IC). The method includes receiving an IC design layout defining a semiconductor structure having a via rail extending lengthwise in a first direction and contacting a source contact extending lengthwise in a second direction perpendicular to the first direction. The method further includes identifying the via rail, the source contact, a drain contact being distanced away from the source contact, and a gate structure interposing the source and drain contacts using pattern recognition on the IC design layout. The method further includes determining a position, length, and width of a jog via to be added to the IC design layout. The method further includes adding the jog via having the pre-determined length and width to the IC design layout at the pre-determined position to provide a modified IC design layout and generating a tape-out for fabricating a modified mask.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES |
| title | Via Rail Structure |
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