PIPELINED SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND METHOD OF ANALOG-TO-DIGITAL CONVERSION

PIPELINED SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND METHOD OF ANALOG-TO-DIGITAL CONVERSION

A pipelined successive approximation register analog-to-digital converter (2), SAR ADC, comprises a first SAR ADC stage (4); an inter-stage amplifier (6) for amplifying an analog residue from the first SAR ADC stage; and a second SAR ADC stage (8) input from the inter-stage amplifier, wherein the in...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: SPAGNOLO, Annachiara
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
PULSE TECHNIQUE
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Beschreibung
Zusammenfassung:A pipelined successive approximation register analog-to-digital converter (2), SAR ADC, comprises a first SAR ADC stage (4); an inter-stage amplifier (6) for amplifying an analog residue from the first SAR ADC stage; and a second SAR ADC stage (8) input from the inter-stage amplifier, wherein the inter-stage amplifier (6) comprises one or more MOS transistors (16, 18), wherein the source and drain terminals of each of the one or more MOS transistors (16, 18) are connected to each other and may be toggled between ground and a supply voltage.