DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT

A delay line includes a first delay cell and a second delay cell. The first delay cell inverts an input signal to generate a first output signal. The second delay cell inverts the first output signal to generate a second output signal. The driving forces of the first delay cell is adjusted on the ba...

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Hauptverfasser:	HAN, Yun Tack, KIM, Kyeong Min
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY
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creator	HAN, Yun Tack KIM, Kyeong Min
description	A delay line includes a first delay cell and a second delay cell. The first delay cell inverts an input signal to generate a first output signal. The second delay cell inverts the first output signal to generate a second output signal. The driving forces of the first delay cell is adjusted on the basis of a delay control voltage and the second output signal.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2021075430A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2021075430A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2021075430A13</originalsourceid><addsrcrecordid>eNrjZKhxcfVxjFTw8fRz1VFwVIDy_J29XV2AlH-AgrNnkHOoZ4iCo58LUD7Y1dfT2d_PJdQ5xD9IwTEgwDHIMSQ0WCE02NPPXSHEw1UBYR5YC5IQpqE8DKxpiTnFqbxQmptB2c01xNlDN7UgPz61uCAxOTUvtSQ-NNjIwMjQwNzUxNjA0dCYOFUAxxs6_Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT</title><source>esp@cenet</source><creator>HAN, Yun Tack ; KIM, Kyeong Min</creator><creatorcontrib>HAN, Yun Tack ; KIM, Kyeong Min</creatorcontrib><description>A delay line includes a first delay cell and a second delay cell. The first delay cell inverts an input signal to generate a first output signal. The second delay cell inverts the first output signal to generate a second output signal. The driving forces of the first delay cell is adjusted on the basis of a delay control voltage and the second output signal.</description><language>eng</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210311&DB=EPODOC&CC=US&NR=2021075430A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210311&DB=EPODOC&CC=US&NR=2021075430A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HAN, Yun Tack</creatorcontrib><creatorcontrib>KIM, Kyeong Min</creatorcontrib><title>DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT</title><description>A delay line includes a first delay cell and a second delay cell. The first delay cell inverts an input signal to generate a first output signal. The second delay cell inverts the first output signal to generate a second output signal. The driving forces of the first delay cell is adjusted on the basis of a delay control voltage and the second output signal.</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZKhxcfVxjFTw8fRz1VFwVIDy_J29XV2AlH-AgrNnkHOoZ4iCo58LUD7Y1dfT2d_PJdQ5xD9IwTEgwDHIMSQ0WCE02NPPXSHEw1UBYR5YC5IQpqE8DKxpiTnFqbxQmptB2c01xNlDN7UgPz61uCAxOTUvtSQ-NNjIwMjQwNzUxNjA0dCYOFUAxxs6_Q</recordid><startdate>20210311</startdate><enddate>20210311</enddate><creator>HAN, Yun Tack</creator><creator>KIM, Kyeong Min</creator><scope>EVB</scope></search><sort><creationdate>20210311</creationdate><title>DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT</title><author>HAN, Yun Tack ; KIM, Kyeong Min</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2021075430A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>HAN, Yun Tack</creatorcontrib><creatorcontrib>KIM, Kyeong Min</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HAN, Yun Tack</au><au>KIM, Kyeong Min</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT</title><date>2021-03-11</date><risdate>2021</risdate><abstract>A delay line includes a first delay cell and a second delay cell. The first delay cell inverts an input signal to generate a first output signal. The second delay cell inverts the first output signal to generate a second output signal. The driving forces of the first delay cell is adjusted on the basis of a delay control voltage and the second output signal.</abstract><oa>free_for_read</oa></addata></record>
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subjects	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY
title	DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T17%3A23%3A03IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HAN,%20Yun%20Tack&rft.date=2021-03-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2021075430A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true