TIMESTAMP-BASED FAIRNESS EGRESS FROM INGRESS QUEUES

Examples described herein provide a packet ingress and egress system with a memory buffer in a network device. The ingress and egress system can generate a time stamp for one or more received packets at an ingress port, allocate a received packet to a queue among multiple queues, and permit egress o...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: DIESING, Scott, GRETH, John, SOUTHWORTH, Robert, MORA PORTA, Gaspar, ARDITTI ILITZKY, David, SRINIVASAN, Arvind, SHABADI, Prasad, JUNG, Bongjin
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Examples described herein provide a packet ingress and egress system with a memory buffer in a network device. The ingress and egress system can generate a time stamp for one or more received packets at an ingress port, allocate a received packet to a queue among multiple queues, and permit egress of a packet from a queue. An ingress port can have one or more queues allocated to store received packets. An egress port can use the one or more queues from which to egress packets. A maximum size of a queue is set as the allocated memory region size divided by the number of ingress ports that use the allocated memory region. An egress arbiter can apply an arbitration scheme to schedule egress of packets in time stamp order.