Power Semiconductor Package and Method for Fabricating a Power Semiconductor Package

Power Semiconductor Package and Method for Fabricating a Power Semiconductor Package

A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating...

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Bibliographische Detailangaben
Hauptverfasser: Sam, Ying Pok, Lim, Wee Aun Jason, Chin, Ting Soon, Chong, Chooi Mei, Calo, Paul Armand Asentista, Murugan, Sanjay Kumar, Tan, Chee Voon
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A power semiconductor package includes a power semiconductor chip, an electrical connector arranged at a first side of the power semiconductor chip and having a first surface that is coupled to a power electrode of the power semiconductor chip, an encapsulation body at least partially encapsulating the power semiconductor chip and the electrical connector, and an electrical insulation layer arranged at a second surface of the electrical connector opposite the first surface, wherein parts of the encapsulation body and the electrical insulation layer form a coplanar surface of the power semiconductor package.