MULTI-HEIGHT INTERCONNECT TRENCHES FOR RESISTANCE AND CAPACITANCE OPTIMIZATION
Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a...
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| creator | ANDERS, Mark KRISHNAMURTHY, Ram LIN, Kevin Lai KOBRINSKY, Mauro KAUL, Himanshu |
| description | Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2021043500A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2021043500A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2021043500A13</originalsourceid><addsrcrecordid>eNqNyjEKwkAQQNE0FqLeYcA6sEn0AMM4cQfMbNidNDYhyFqJBuL9sdADWH0e_HWh3XAxKT3L2RuIGkcKqkwGFlnJc4I2RIicJBkqMaCegLBHkq9Db9LJFU2CbovVfXoseffrpti3bOTLPL_GvMzTLT_zexxS7erKHZqjc1g1_10f92ovog</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MULTI-HEIGHT INTERCONNECT TRENCHES FOR RESISTANCE AND CAPACITANCE OPTIMIZATION</title><source>esp@cenet</source><creator>ANDERS, Mark ; KRISHNAMURTHY, Ram ; LIN, Kevin Lai ; KOBRINSKY, Mauro ; KAUL, Himanshu</creator><creatorcontrib>ANDERS, Mark ; KRISHNAMURTHY, Ram ; LIN, Kevin Lai ; KOBRINSKY, Mauro ; KAUL, Himanshu</creatorcontrib><description>Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210211&DB=EPODOC&CC=US&NR=2021043500A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210211&DB=EPODOC&CC=US&NR=2021043500A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>ANDERS, Mark</creatorcontrib><creatorcontrib>KRISHNAMURTHY, Ram</creatorcontrib><creatorcontrib>LIN, Kevin Lai</creatorcontrib><creatorcontrib>KOBRINSKY, Mauro</creatorcontrib><creatorcontrib>KAUL, Himanshu</creatorcontrib><title>MULTI-HEIGHT INTERCONNECT TRENCHES FOR RESISTANCE AND CAPACITANCE OPTIMIZATION</title><description>Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjEKwkAQQNE0FqLeYcA6sEn0AMM4cQfMbNidNDYhyFqJBuL9sdADWH0e_HWh3XAxKT3L2RuIGkcKqkwGFlnJc4I2RIicJBkqMaCegLBHkq9Db9LJFU2CbovVfXoseffrpti3bOTLPL_GvMzTLT_zexxS7erKHZqjc1g1_10f92ovog</recordid><startdate>20210211</startdate><enddate>20210211</enddate><creator>ANDERS, Mark</creator><creator>KRISHNAMURTHY, Ram</creator><creator>LIN, Kevin Lai</creator><creator>KOBRINSKY, Mauro</creator><creator>KAUL, Himanshu</creator><scope>EVB</scope></search><sort><creationdate>20210211</creationdate><title>MULTI-HEIGHT INTERCONNECT TRENCHES FOR RESISTANCE AND CAPACITANCE OPTIMIZATION</title><author>ANDERS, Mark ; KRISHNAMURTHY, Ram ; LIN, Kevin Lai ; KOBRINSKY, Mauro ; KAUL, Himanshu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2021043500A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>ANDERS, Mark</creatorcontrib><creatorcontrib>KRISHNAMURTHY, Ram</creatorcontrib><creatorcontrib>LIN, Kevin Lai</creatorcontrib><creatorcontrib>KOBRINSKY, Mauro</creatorcontrib><creatorcontrib>KAUL, Himanshu</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>ANDERS, Mark</au><au>KRISHNAMURTHY, Ram</au><au>LIN, Kevin Lai</au><au>KOBRINSKY, Mauro</au><au>KAUL, Himanshu</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MULTI-HEIGHT INTERCONNECT TRENCHES FOR RESISTANCE AND CAPACITANCE OPTIMIZATION</title><date>2021-02-11</date><risdate>2021</risdate><abstract>Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | MULTI-HEIGHT INTERCONNECT TRENCHES FOR RESISTANCE AND CAPACITANCE OPTIMIZATION |
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