MULTI-HEIGHT INTERCONNECT TRENCHES FOR RESISTANCE AND CAPACITANCE OPTIMIZATION

MULTI-HEIGHT INTERCONNECT TRENCHES FOR RESISTANCE AND CAPACITANCE OPTIMIZATION

Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: ANDERS, Mark, KRISHNAMURTHY, Ram, LIN, Kevin Lai, KOBRINSKY, Mauro, KAUL, Himanshu
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.