SEMICONDUCTOR STRUCTURE AND METHOD OF FORMATION

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMATION

The present disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes a substrate, a first device, a second device, a fin, a first gate dielectric layer, a second gate dielectric layer, and a cut region of the fin. The second device is adjac...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: CHOU, YI-HSIEN
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator CHOU, YI-HSIEN
description The present disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes a substrate, a first device, a second device, a fin, a first gate dielectric layer, a second gate dielectric layer, and a cut region of the fin. The second device is adjacent to the first device. The fin is disposed on the substrate between the first device and the second device. The first gate dielectric layer is disposed on a first portion of the fin, and the second gate dielectric layer is disposed on a second portion of the fin. The cut region of the fin is formed within a trench between the first device and the second device.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2021020635A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2021020635A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2021020635A13</originalsourceid><addsrcrecordid>eNrjZNAPdvX1dPb3cwl1DvEPUggOCQIyQoNcFRz9XBR8XUM8_F0U_N0U3PyDfB1DPP39eBhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGRoYGRgZmxqaOhMXGqAL-dJxw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR STRUCTURE AND METHOD OF FORMATION</title><source>esp@cenet</source><creator>CHOU, YI-HSIEN</creator><creatorcontrib>CHOU, YI-HSIEN</creatorcontrib><description>The present disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes a substrate, a first device, a second device, a fin, a first gate dielectric layer, a second gate dielectric layer, and a cut region of the fin. The second device is adjacent to the first device. The fin is disposed on the substrate between the first device and the second device. The first gate dielectric layer is disposed on a first portion of the fin, and the second gate dielectric layer is disposed on a second portion of the fin. The cut region of the fin is formed within a trench between the first device and the second device.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210121&amp;DB=EPODOC&amp;CC=US&amp;NR=2021020635A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210121&amp;DB=EPODOC&amp;CC=US&amp;NR=2021020635A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHOU, YI-HSIEN</creatorcontrib><title>SEMICONDUCTOR STRUCTURE AND METHOD OF FORMATION</title><description>The present disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes a substrate, a first device, a second device, a fin, a first gate dielectric layer, a second gate dielectric layer, and a cut region of the fin. The second device is adjacent to the first device. The fin is disposed on the substrate between the first device and the second device. The first gate dielectric layer is disposed on a first portion of the fin, and the second gate dielectric layer is disposed on a second portion of the fin. The cut region of the fin is formed within a trench between the first device and the second device.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAPdvX1dPb3cwl1DvEPUggOCQIyQoNcFRz9XBR8XUM8_F0U_N0U3PyDfB1DPP39eBhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGRoYGRgZmxqaOhMXGqAL-dJxw</recordid><startdate>20210121</startdate><enddate>20210121</enddate><creator>CHOU, YI-HSIEN</creator><scope>EVB</scope></search><sort><creationdate>20210121</creationdate><title>SEMICONDUCTOR STRUCTURE AND METHOD OF FORMATION</title><author>CHOU, YI-HSIEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2021020635A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHOU, YI-HSIEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHOU, YI-HSIEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR STRUCTURE AND METHOD OF FORMATION</title><date>2021-01-21</date><risdate>2021</risdate><abstract>The present disclosure provides a semiconductor structure and a method of forming the same. The semiconductor structure includes a substrate, a first device, a second device, a fin, a first gate dielectric layer, a second gate dielectric layer, and a cut region of the fin. The second device is adjacent to the first device. The fin is disposed on the substrate between the first device and the second device. The first gate dielectric layer is disposed on a first portion of the fin, and the second gate dielectric layer is disposed on a second portion of the fin. The cut region of the fin is formed within a trench between the first device and the second device.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2021020635A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR STRUCTURE AND METHOD OF FORMATION
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T02%3A17%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHOU,%20YI-HSIEN&rft.date=2021-01-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2021020635A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true