EXECUTION UNIT ACCELERATOR

EXECUTION UNIT ACCELERATOR

A processor to facilitate acceleration of instruction execution is disclosed. The processor includes a plurality of execution units (EUs), each including an instruction decode unit to decode an instruction into one or more operands and opcode defining an operation to be performed at an accelerator,...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Sripada, Radhakrishna, Yiannacouras, Peter, Chitlur, Nagabhushan, Triplett, Josh, Kondapally, Kalyan
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
PHYSICS
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Beschreibung
Zusammenfassung:A processor to facilitate acceleration of instruction execution is disclosed. The processor includes a plurality of execution units (EUs), each including an instruction decode unit to decode an instruction into one or more operands and opcode defining an operation to be performed at an accelerator, a register file having a plurality of registers to store the one or more operands and an accelerator having programmable hardware to retrieve the one or more operands from the register file and perform the operation on the one or more operands.