SRAM BITCELL SUPPLY BLOCK WITH MULTIPLE OPERATING MODES

A power-supply circuit for a memory includes a bitcell power-supply circuit and a bitcell power-control circuit. The bitcell power-supply circuit includes a first terminal coupled to a bitcell of the memory. The bitcell power-control circuit is coupled to the bitcell power-supply circuit, and controls the bitcell power-supply circuit in a write-assist mode to output a first voltage on the first terminal that is based on a ratio of capacitance of the bitcell and of capacitance of a charge-sharing capacitance. The bitcell power-control circuit further controls the bitcell power-supply circuit in a data-retention mode to output a second voltage on the first terminal that is about one diode drop below a voltage of a main power supply to the bitcell. The bitcell power-control circuit also controls the bitcell power-supply circuit in a power-down mode to turn off power output from the first terminal.