METHOD AND SYSTEM FOR MANUFACTURING A SEMICONDUCTOR DEVICE

The present disclosure provides a method for manufacturing a semiconductor structure. The method includes receiving a layout data representing information for manufacturing the semiconductor structure having a metal layer over a substrate. A first parasitic capacitance and a second parasitic capacitance are formed between the metal layer and the substrate. The method further includes determining a parasitic capacitance difference between a first region and a second region. The method further includes forming a dummy capacitor to minimize the parasitic capacitance difference. A system for manufacturing a semiconductor device is also provided.