PARALLEL PATH DELAY LINE

Circuitry and methods of operating the same to delay a signal by a precise and variable amount. One embodiment is directed to a high speed delay line used in automated test equipment. The inventors have recognized and appreciated that an input signal having high data rate may be split into parallel split signals having lower data rates that are delayed in respective parallel delay paths before being combined to generate a delayed signal. One advantage of delaying a signal in such a fashion is to provide high delay line timing accuracy at high data speeds, while using a compact circuit design using circuitry components of lower bandwidth with reduced power consumption, for example by using complementary metal-oxide-semiconductor (CMOS). A further advantage is that a high speed delay line may be constructed from multiple lower data rate parallel delay lines that are modular, simplifying circuit design.