Leaded Semiconductor Package

A semiconductor package includes a mold compound, a plurality of electrically conductive leads at least some of which transition from a first level within the mold compound to a second (different) level outside the mold compound, and a semiconductor die embedded in the mold compound and attached to...

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Hauptverfasser: Mohamad Tahir, Mohd Rasydan Hakam, Pavaluta, Ciprian Mircea, Lee, Swee Kah, Muhammat Sanusi, Muhammad, Kim, Do Hyung, Othman, Nurfarena
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creator Mohamad Tahir, Mohd Rasydan Hakam
Pavaluta, Ciprian Mircea
Lee, Swee Kah
Muhammat Sanusi, Muhammad
Kim, Do Hyung
Othman, Nurfarena
description A semiconductor package includes a mold compound, a plurality of electrically conductive leads at least some of which transition from a first level within the mold compound to a second (different) level outside the mold compound, and a semiconductor die embedded in the mold compound and attached to the plurality of electrically conductive leads in a flip-chip configuration. One or more leads of the plurality of electrically conductive leads includes a first section terminating at a side face of the mold compound or protruding from the side face with a first end positioned outside a footprint of the mold compound and which terminates at the second level, and a second section embedded in the mold compound and having a second end which is positioned under the semiconductor die and exposed at a bottom side of the semiconductor package. Corresponding methods of manufacture are also described.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2020343167A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2020343167A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2020343167A13</originalsourceid><addsrcrecordid>eNrjZJDxSU1MSU1RCE7NzUzOz0spTS7JL1IISEzOTkxP5WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGBsYmxoZm5o6GxsSpAgAZkyR5</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Leaded Semiconductor Package</title><source>esp@cenet</source><creator>Mohamad Tahir, Mohd Rasydan Hakam ; Pavaluta, Ciprian Mircea ; Lee, Swee Kah ; Muhammat Sanusi, Muhammad ; Kim, Do Hyung ; Othman, Nurfarena</creator><creatorcontrib>Mohamad Tahir, Mohd Rasydan Hakam ; Pavaluta, Ciprian Mircea ; Lee, Swee Kah ; Muhammat Sanusi, Muhammad ; Kim, Do Hyung ; Othman, Nurfarena</creatorcontrib><description>A semiconductor package includes a mold compound, a plurality of electrically conductive leads at least some of which transition from a first level within the mold compound to a second (different) level outside the mold compound, and a semiconductor die embedded in the mold compound and attached to the plurality of electrically conductive leads in a flip-chip configuration. One or more leads of the plurality of electrically conductive leads includes a first section terminating at a side face of the mold compound or protruding from the side face with a first end positioned outside a footprint of the mold compound and which terminates at the second level, and a second section embedded in the mold compound and having a second end which is positioned under the semiconductor die and exposed at a bottom side of the semiconductor package. Corresponding methods of manufacture are also described.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20201029&amp;DB=EPODOC&amp;CC=US&amp;NR=2020343167A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20201029&amp;DB=EPODOC&amp;CC=US&amp;NR=2020343167A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Mohamad Tahir, Mohd Rasydan Hakam</creatorcontrib><creatorcontrib>Pavaluta, Ciprian Mircea</creatorcontrib><creatorcontrib>Lee, Swee Kah</creatorcontrib><creatorcontrib>Muhammat Sanusi, Muhammad</creatorcontrib><creatorcontrib>Kim, Do Hyung</creatorcontrib><creatorcontrib>Othman, Nurfarena</creatorcontrib><title>Leaded Semiconductor Package</title><description>A semiconductor package includes a mold compound, a plurality of electrically conductive leads at least some of which transition from a first level within the mold compound to a second (different) level outside the mold compound, and a semiconductor die embedded in the mold compound and attached to the plurality of electrically conductive leads in a flip-chip configuration. One or more leads of the plurality of electrically conductive leads includes a first section terminating at a side face of the mold compound or protruding from the side face with a first end positioned outside a footprint of the mold compound and which terminates at the second level, and a second section embedded in the mold compound and having a second end which is positioned under the semiconductor die and exposed at a bottom side of the semiconductor package. Corresponding methods of manufacture are also described.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJDxSU1MSU1RCE7NzUzOz0spTS7JL1IISEzOTkxP5WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGBsYmxoZm5o6GxsSpAgAZkyR5</recordid><startdate>20201029</startdate><enddate>20201029</enddate><creator>Mohamad Tahir, Mohd Rasydan Hakam</creator><creator>Pavaluta, Ciprian Mircea</creator><creator>Lee, Swee Kah</creator><creator>Muhammat Sanusi, Muhammad</creator><creator>Kim, Do Hyung</creator><creator>Othman, Nurfarena</creator><scope>EVB</scope></search><sort><creationdate>20201029</creationdate><title>Leaded Semiconductor Package</title><author>Mohamad Tahir, Mohd Rasydan Hakam ; Pavaluta, Ciprian Mircea ; Lee, Swee Kah ; Muhammat Sanusi, Muhammad ; Kim, Do Hyung ; Othman, Nurfarena</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2020343167A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Mohamad Tahir, Mohd Rasydan Hakam</creatorcontrib><creatorcontrib>Pavaluta, Ciprian Mircea</creatorcontrib><creatorcontrib>Lee, Swee Kah</creatorcontrib><creatorcontrib>Muhammat Sanusi, Muhammad</creatorcontrib><creatorcontrib>Kim, Do Hyung</creatorcontrib><creatorcontrib>Othman, Nurfarena</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mohamad Tahir, Mohd Rasydan Hakam</au><au>Pavaluta, Ciprian Mircea</au><au>Lee, Swee Kah</au><au>Muhammat Sanusi, Muhammad</au><au>Kim, Do Hyung</au><au>Othman, Nurfarena</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Leaded Semiconductor Package</title><date>2020-10-29</date><risdate>2020</risdate><abstract>A semiconductor package includes a mold compound, a plurality of electrically conductive leads at least some of which transition from a first level within the mold compound to a second (different) level outside the mold compound, and a semiconductor die embedded in the mold compound and attached to the plurality of electrically conductive leads in a flip-chip configuration. One or more leads of the plurality of electrically conductive leads includes a first section terminating at a side face of the mold compound or protruding from the side face with a first end positioned outside a footprint of the mold compound and which terminates at the second level, and a second section embedded in the mold compound and having a second end which is positioned under the semiconductor die and exposed at a bottom side of the semiconductor package. Corresponding methods of manufacture are also described.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Leaded Semiconductor Package
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-24T20%3A13%3A03IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Mohamad%20Tahir,%20Mohd%20Rasydan%20Hakam&rft.date=2020-10-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2020343167A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true