METHOD OF FAST ERASING AN EEPROM WITH LOW-VOLTAGES, WHERE IONS ARE IMPLANTED AT A HIGHER CONCENTRATION TO INCREASE THE INTENSITY OF THE ELECTRIC FIELD BETWEEN THE GATE AND THE SUBSTRATE OR BETWEEN THE GATE AND THE TRANSISTOR AND THUS DECREASE THE REQUIRED VOLTAGE DIFFERENCE FOR ERASING THE EEPROM

The present invention discloses a method of fast erasing an EEPROM with low-voltages. The EEPROM includes a transistor structure is formed in a semiconductor substrate and the transistor structure includes a first electric-conduction gate. Same type ions are implanted into a region of the semiconductor substrate, which is near interfaces of a source, a drain and the first electric-conduction gate, or ion-doped regions of the source and the drain, to increase the ion concentration thereof, whereby to reduce the voltage differences required for erasing. Moreover, the source or the drain is floated during erasing to achieve rapid erasing for a large number of memory cells. In addition to the EEPROM with a single gate transistor structure, the present invention also applies to the EEPROM with a single floating gate transistor structure.