POLISHING PAD THAT MINIMIZES OCCURRENCE OF DEFECTS AND PROCESS FOR PREPARING THE SAME

POLISHING PAD THAT MINIMIZES OCCURRENCE OF DEFECTS AND PROCESS FOR PREPARING THE SAME

The present invention relates to a polishing pad that minimizes the occurrence of defects and a process for preparing the same, Since the polishing pad comprises fine hollow particles having shells, the glass transition temperature (Tg) of which is adjusted, the hardness of the shells and the shape...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: YUN, Sunghoon, SEO, Jang Won, YUN, Jong Wook, HEO, Hye Young, AHN, Jaein
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
DRESSING OR CONDITIONING OF ABRADING SURFACES
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
GRINDING
MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING
PERFORMING OPERATIONS
POLISHING
SEMICONDUCTOR DEVICES
TRANSPORTING
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Beschreibung
Zusammenfassung:The present invention relates to a polishing pad that minimizes the occurrence of defects and a process for preparing the same, Since the polishing pad comprises fine hollow particles having shells, the glass transition temperature (Tg) of which is adjusted, the hardness of the shells and the shape of micropores on the surface of a polishing layer are controlled. Since the content of Si in the polishing layer is adjusted, it is possible to prevent the surface damage of a semiconductor substrate caused by hard additives. As a result, the polishing pad can provide a high polishing rate while minimizing the occurrence of defects such as scratches on the surface of a semiconductor substrate during the CMP process.